Background
Of the many different kinds of integrated circuit memories, the dynamic random access memory (DRAM) is the commonest. FIG. 1 shows a block diagram of an early DRAM chip, showing some of the basic architecture. In this drawing, memory array 161 is divided into two parts, A and B, with associated sense amplifiers 162 adjacent the array. Addresses to be accessed are received in the address input buffer 163 and are sent to the row decoder 164 and column decoder 165. Data to be stored is received on the data-in buffer 166, and data to be output is sent to the data-out buffer 167.
At the level of the DRAM array itself, seen in FIG. 2, memory cells are arranged in rows (also called word lines) and columns (bit lines). Each cell can be referenced by its unique word line/bit line address, with each Cellx,y including a storage capacitor Cx,y and a pass transistor Tx,y to provide access to the capacitor. When the pass transistor is turned on, it connects the capacitor to a bit line, which in turn connects the selected cell in a given column to a sense amplifier. The bit lines are arranged as complementary pairs (commonly referred to as a digit and digit bar pair), and each pair is attached to a p-sense amplifier and an n-sense amplifier (which together are often referred to as simply a sense amplifier). In the array shown, even numbered digit pairs (BL0A/BL0B and BL2A/BL2B) would be connected to sense amplifiers at the bottom of the array, while odd numbered digit pairs (BL1A/BL1B and BL3A/BL3B) would be connected to sense amplifiers at the top of the array. The p-sense amplifier, seen in FIG. 3, is composed of two cross-coupled p-channel transistors 1410 and 1420. Likewise, an n-sense amplifier, seen in FIG. 4, is composed of cross-coupled n-channel transistors 1310 and 1320. The p-channel and n-channel sense amplifiers together form a bi-stable latch which may be fired or floated by controlling connections to high and low potentials. When the cell is accessed for a read or refresh operation, the sense amplifier amplifies the very weak signal from the cell capacitor to provide a useable output signal, and restore the voltage on the capacitor to its maximum high or low value.
In a precharged state, all word lines are at a low level, keeping all storage capacitors isolated from their respective bit lines by the access transistors. All of the bit lines are held at a level typically midway between the high and low potential and shorted together in pairs by an equilibration circuit (not shown).
In operation, the following events take place sequentially: (a) a word line is taken high, allowing a charge share to take place between the storage capacitors of the selected cells and one of each bit line pair; (b) the sharing of charge from the storage capacitors causes a small change higher or lower in the level of the connected digit, which then is at a different level than the other digit in the digit pair; (c) the sense amplifiers are fired, pulling the lower of the two digits comprising a digit pair to the low potential and the higher digit to the high potential; (d) reads (or writes) may reference (or change) the latched state of the digit pair and sense amplifiers; (e) the word line is returned to the low precharged state; and (f) the sense amplifiers are floated and the digit lines are shorted to their original starting state.
One of the possible sources of errors in a dense memory array is externally received transient signals. Another is cross-coupling: whenever two closely-spaced conductors run in parallel for a significant distance, a certain degree of parasitic coupling will exist between the conductors. To alleviate both of these problems, one common architecture is xe2x80x9ctwistedxe2x80x9d bit lines. This is generally accomplished by taking two adjacent bit line pairs (e.g., BL0A/BL0B and BL1A/BL1B) and causing them to cross over each other so that the same bit lines are not adjacent to each other for their entire length. This twisting is evident in FIG. 2.
One inconvenient result of the progress in shrinking memory cells is that the xe2x80x9cpitchxe2x80x9d of a memory array (i.e., the center-to-center spacing between adjacent columns or adjacent rows) can become too small to contain the needed peripheral circuits. An example of this is seen in the sense amplifiers used to read the cells. Where previously a sense amplifier could be constructed within the width of a bit line pair, the decreasing pitch of shrinking DRAM arrays now means that a sense amplifier needs the width of two bit line pairs for its construction. This is generally handled by putting sense amplifiers at both ends of the array, with one half of the bit line pair being connected to sense amplifiers at a first end of the array, and a second half of the bit line pairs being connected to sense amplifiers at the other end.
As memory cells have continued to shrink, one constraint which becomes more important is parasitic capacitance. As the size of individual cells is reduced, the strength of the electrical signals associated with them is also reduced. At the same time, the number of cells attached to a bit line increases and the length of the bit line itself gets longer, which increases the parasitic capacitance associated with the bit line. With a lower capacitance on the cell and a higher capacitance on the bit line, it takes longer for a useful signal to develop on the line, which slows the response time of the memory, a critical factor. An additional effect of this shrinking capacitance ratio is that the potential difference between digits which the sense amplifier must detect becomes smaller.
One approach which has been tried to reduce bit line capacitance is segmented bit lines. In this approach, the individual cells are not connected to the entire bit line but merely connected to a segment. Segment selection switches connect the appropriate segment for a selected cell to the bit line and to the sense amplifier. However, this approach requires additional area for the segment selection switches and typically also requires an additional layer of metallization.
Another approach is to use isolation gates. U.S. Pat. No. 5,369,622 to McLaury, which is commonly owned by the assignee of this application, explains how an older, single pitched sense amplifier memory can be made to save power by controlling existing isolation devices in a novel manner by isolating unnecessary portions of the bit line during read/write operations. FIG. 5 shows an example of a bit line pair in array Ax, such as is shown in this patent. This array contains a single n-sense amplifier for each digit pair, but two p-sense amplifiers at either end of the array Ax, each used with either subarray A or subarray B. Although this drawing shows a single bit line, the same layout is repeated across the array. Isolation lines isolate_a and isolate_b selectively isolate the non-selected subarray (and its associated p-sense amplifier) from the n-sense amplifier, which is still connected to the selected subarray and its associated p-sense amplifier. This isolation favorably changes the capacitance ratio between the bit line and the cell being read/written, but since the I/O path is connected to only one end of the bit line, it is necessary to turn on the isolation devices to allow full connection of the bit line to I/O devices. McLaury recognized that if the selected cells were in the subarray which was directly connected to the I/O path, then it was possible to save power by controlling the timing on existing isolation devices so that the subarray which was distant from the I/O is kept isolated when it was not involved in the read/write operation.
However, virtually all DRAM memories are now made with dual pitched sense amplifiers shared between two array blocks. An example of this is seen in FIG. 6. In this drawing, a row of n-sense amplifiers and p-sense amplifiers are placed between two arrays Ax and Ay, with n- and p-sense amplifier being shared between a digit pair in Ax and a digit pair in Ay. This drawing shows only every other digit pair being connected to the sense amplifiers; each array will have a further row of shared sense amplifiers located at the other end of the bit lines for connection to the remaining digit pairs. Isolation lines isolate_x and isolate_y are used to select which of array blocks Ax or Ay will be active in a given cycle, with no provision being made for isolation lines to separate subarrays. This strategy does not allow the power savings which was afforded by McLaury.
In one embodiment, a memory array includes a first half and a second half, each half having a number of memory cells accessed by word lines and bit lines. The first half is connected to a number of first half sense amplifiers, and the second half is connected to a number of second half sense amplifiers. Isolation transistors connected between the first and the second halves are controlled to isolate portions of parts of the first half bit lines connected to the second half sense amplifiers when a second half word line is used, and to isolate portions of parts of the second half bit lines connected to the first half sense amplifiers when a first half word line is used.
In another embodiment, a memory device includes a number of even bit lines and a number of odd bit lines, the even bit lines connected to a first set of sense amplifiers on one side of the array and the odd bit lines connected to a second set of sense amplifiers on another side of the array, and a number of first half and second half word lines. A first isolate line and a second isolate line are connected to prevent signal transmission between the first and the second halves on one of the sets of bit lines when a word line is accessed.
In yet another embodiment, a method of reducing power consumption in a memory circuit includes isolating a number of sense amplifiers connected to bit lines of a near subarray and a far subarray from the far subarray, initiating a memory operation using a word line of the near array during isolation of the far subarray.
Other embodiments are described and claimed.